As detailed in the  Zorro II Compatibility  section, the Zorro III bus
supports a bus cycle mode very similar to the  68000-based Zorro II bus ,
and is expected to be compatible with all properly designed Zorro II PICs.
As shown in  Figure K-1 , Zorro II and Zorro III expansion spaces are
geographically mapped on the Zorro III bus. The mapping logic resides on
the bus, and operates on the bus address presented for any cycle.  Every
cycle starts out assuming a Zorro III cycle, but the mapping logic will
inscribe a Zorro II cycle within the Zorro III cycle if the address range
is right. Figure K-9 details the bus action for this mode.


           _____        READ CYCLE       ___       WRITE CYCLE        __
      /FCS      \                       /   \                        /
                 \_____________________/     \______________________/

                    /FCS sample edge
           __    __ /  __    __    __    __    __    __    __    __    _
      CDAC   |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
             |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|

            /DTACK sample edge        data latch edge
           _    __    __    __\   __ /  __    __    __    __    __    __
        7M  |  |30|  |32|  |34|  |36|  |  |  |30|  |32|  |34|  |36|  |
            |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|
                   31    33    35    37          31    33    35    37
           __________                 ____________                 _____
      /CCS           \               /            \               /
                      \_____________/              \_____________/

              address   data from slave   address    data from master
                _|_     ____________|__     _|_      _______|________
AD31..AD24 ____/ | \___/         /  |  \___/ | \____/       |        \__
               \___/   \_________\_____/   \___/    \________________/
                ______________________      _________________________
 AD23..AD8 ____/                      \____/                         \__
  SA7..SA2     \______________________/    \_________________________/
           ________________________________                           __
      READ    /                            \                         /
           __/                              \_______________________/
           _____________             _________________              ____
    /SLAVE              \           /                 \            /
                         \_________/                   \__________/
                              _______                        _______
       DOE                   /       \                      /       \
           _________________/         \____________________/         \__
           __________               _______________________        _____
 /DS3,/DS2           \             /                       \      /
                      \___________/                         \____/
           ___________________        _______________________        ___
    /DTACK                    \      /                       \      /
                               \____/                         \____/


                   Figure K-9 Zorro II Within Zorro III


The cycle starts out with the usual address phase activity; the bus master
asserts  /FCS  after asserting the full 32-bit address onto the address
bus. The bus decoder maps the bus address  asynchronously  and quickly, so
that by the time  /FCS  is asserted, the memory space is determined.  A
Zorro II space access will cause  A8-A23  to remain asserted, rather than
being tri-stated along with  A24-A31 , as the Zorro III cycle normally
does. The bus controller synchs the  asynchronous   /FCS  on the falling
edge of CDAC, then drives  /CCS  (the  /AS  equivalent) out on the rising
edge of  7M , based on that synched  /FCS . For a read cycle,  /DS3 
and/or  /DS2  (the  /UDS  and  /LDS  replacements, respectively) would be
asserted along with  /CCS ; write cycles see those lines asserted on the
next rising edge of  7M , at S4 time. The  DOE  line is also asserted at
the start of S4.

The bus controller starts to sample  /DTACK  on the falling edge of  7M 
between S4 and S5, adding wait states until  /DTACK  is encountered. As
per Zorro II specs, the PIC need not create a  /DTACK  unless it needs
that level of control; there are Zorro II signals to delay the
controller-generated  /DTACK , or take it over when necessary.  The
controller will drive its automatic  /DTACK  at the start of S4, leaving
plenty of time for the sampling to come at S5.  Once a  /DTACK  is
encountered, cycle  termination  begins.  The controller latches data on
the falling  7M  edge between S6 and S7, and also negates  /CCS  and the
 /DSn  at this time. Shortly thereafter, the controller negates  /DTACK 
(when controlling it),  DOE , and tri-states the data bus, getting ready
for the next cycle.

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