Agnus/
                  Read/   Denise/
Register Address  Write   Paula         Function
-------- -------  -----   -------       --------
COPINS     08C      W       A     Copper instruction fetch identify

                 This is a dummy address that is generated by the
                 Copper whenever it is loading instructions into
                 its own instruction register. This actually occurs
                 every Copper cycle except for the second (IR2)
                 cycle of the MOVE instruction. The three types
                 of instructions are shown below.

                 MOVE    Move immediate to destination.
                 WAIT    Wait until beam counter is equal to, or
                         greater than.  (keeps Copper off of bus
                         until beam position has been reached).
                 SKIP    Skip if beam counter is equal to or greater
                         than (skips following MOVE instruction unless
                         beam position has been reached).

                           MOVE         WAIT UNTIL      SKIP IF
                         --------       -----------    ------------
                 BIT#    IR1   IR2      IR1    IR2     IR1     IR2
                 ----    ----  ----     ----   ----    ----    ----
                 15       X    RD15     VP7    BFD *   VP7    BFD *
                 14       X    RD14     VP6    VE6     VP6    VE6
                 13       X    RD13     VP5    VE5     VP5    VE5
                 12       X    RD12     VP4    VE4     VP4    VE4
                 11       X    RD11     VP3    VE3     VP3    VE3
                 10       X    RD10     VP2    VE2     VP2    VE2
                 09       X    RD09     VP1    VE1     VP1    VE1
                 08      DA8   RD08     VP0    VE0     VP0    VE0
                 07      DA7   RD07     HP8    HE8     HP8    HE8
                 06      DA6   RD06     HP7    HE7     HP7    HE7
                 05      DA5   RD05     HP6    HE6     HP6    HE6
                 04      DA4   RD04     HP5    HE5     HP5    HE5
                 03      DA3   RD03     HP4    HE4     HP4    HE4
                 02      DA2   RD02     HP3    HE3     HP3    HE3
                 01      DA1   RD01     HP2    HE2     HP2    HE2
                 00       0    RD00      1      0       1      1

                 IR1=First instruction register
                 IR2=Second instruction register
                 DA =Destination address for MOVE instruction.  Fetched
                     during IR1 time, used during IR2 time on RGA bus.
                 RD =RAM data moved by MOVE instruction at IR2 time
                     directly from RAM to the address given by the
                     DA field.
                 VP =Vertical beam position comparison bit.
                 HP =Horizontal beam position comparison bit.
                 VE =Enable comparison (mask bit).
                 HE =Enable comparison (mask bit).

                * NOTE BFD=Blitter finished disable. When this bit
                           is true, the Blitter Finished flag will
                           have no effect on the Copper. When this
                           bit is zero, the Blitter Finished flag
                           must be true (in addition to the rest of
                           the bit comparisons) before the Copper
                           can exit from its wait state or skip
                           over an instruction.  Note that the V7
                           comparison cannot be masked.

                 The Copper is basically a two-cycle machine that
                 requests the bus only during odd memory cycles
                 (4 memory cycles per instruction).  This prevents
                 collisions with display, audio, disk, refresh, and
                 sprites, all of which use only even cycles.  It
                 therefore needs (and has) priority over only the
                 blitter and microprocessor.

                 There are only three types of instructions:
                 MOVE immediate, WAIT until, and SKIP if.  All
                 instructions (except for WAIT) require two bus
                 cycles (and two instruction words).  Since only
                 the odd bus cycles are requested, four memory
                 cycle times are required per instruction
                 (memory cycles are 280 ns.)

                 There are two indirect jump registers,  COP1LC  and
                  COP2LC .  These are 18-bit pointer registers whose
                 contents are used to modify the program counter for
                 initialization or jumps.  They are transferred to
                 the program counter whenever strobe addresses
                  COPJMP1  or  COPJMP2  are written.  In addition,
                  COP1LC  is automatically used at the beginning of
                 each vertical blank time.

                 It is important that one of the jump registers be
                 initialized and its jump strobe address hit after
                 power-up but before Copper DMA is initialized.
                 This insures a determined startup address and state.

[Back to Amiga Developer Docs]